1. Field of the Invention
The present invention relates generally to synchronizing the timing of data transfer with a system clock using a delay lock loop. More particularly, the present invention relates to phase-locking to both the rising and the falling edges of the system clock by adding to or subtracting additional compensating delays from the falling edge of an internal clock.
2. State of the Art
Modern high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through, and out of the devices. Additionally, new types of circuit architectures such as RAMBUS and synchronous link dynamic random access memory (SLDRAM) require individual parts to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of a part through the generation of local clock signals has become increasingly more important. Conventionally, data transfer operations are initiated at the edges of the clock signals (i.e., transitions from high to low or low to high).
In synchronous systems, integrated circuits are synchronized to a common system reference clock. This synchronization often cannot be achieved simply by distributing a single system clock to each of the integrated circuits for the following reason, among others. When an integrated circuit receives a system clock, the circuit often must condition the system clock before the circuit can use the clock. For example, the circuit may buffer the incoming system clock or may convert the incoming system clock from one voltage level to another. This processing introduces its own delay, with the result that the locally processed system clock, often will no longer be adequately synchronized with the incoming system clock. The trend toward faster system clock speeds further aggravates this problem since faster clock speeds reduce the amount of delay, or clock skew, which can be tolerated.
To remedy this problem, an additional circuit is conventionally used to synchronize the local clock to the system clock. Two common circuits which are used for this purpose are the phase-locked loop (PLL) and the delay-locked loop (DLL). In the phase-locked loop, a voltage-controlled oscillator produces the local clock. The phases of the local clock and the system clock are compared by a phase-frequency detector, with the resulting error signal used to drive the voltage-controlled oscillator via a loop filter. The feedback via the loop filter phase locks the local clock to the system clock. The delay-locked loop generates a synchronized local clock by delaying the incoming system clock by an integer number of periods. More specifically, the buffers, voltage level converters, etc., of the integrated circuit introduce a certain amount of delay. The delay-locked loop introduces an additional amount of delay such that the resulting local clock is synchronous with the incoming system clock.
In double data rate (DDR) dynamic random access memory (DRAM), wherein operations are initiated on both the rising and the falling edges of the clock signals, it is known to employ a delay lock loop (DDL) to synchronize the output data with the system clock (XCLK) using a phase detector. In an ideal case, the rising edge data is perfectly aligned with the rising edge of the XCLK, the falling edge data is perfectly aligned with the falling edge of the XCLK, and the tAC, or time from when a transition occurs on the XCLK to the time when the data comes through the synchronizing data output (DQ), is within specifications. To approximate an ideal system, a phase detector is conventionally used to lock the rising edge of the DQ signal to the rising edge of the XCLK. In the ideal system, as a result of the rising edge of the DQ signal being phase-locked to the rising edge of the XCLK, the falling edge of the DQ signal changes phase at the same time as the XCLK, or at least within an allowed tolerance (tAC).
FIG. 1 depicts a DDR DRAM data synchronizing circuit using a DLL as is presently contemplated in the art. At system initialization, a phase detector 2 is activated by an initialization signal 4. The phase detector 2 compares the phase of a signal on the CLKIN signal line 6, a derivative of the signal on the XCLK signal line 8, with a signal on the OUT—MDL signal line 10, a model of the data output timing signal. The phase detector 2 then adjusts the DLL delay elements 12 using right shift and left shift signals, on respective ShiftR 14 and ShiftL 16 signal lines, to respectively decrease or increase the time delay added to the CLKIN signal 7 (FIG. 2) on the CLKIN signal line 6 with respect to the OUT—MDL signal 11 (FIG. 2) on the OUT—MDL signal line 10. By adjusting the delay of the signal on the CLKIN signal line 6 through the DLL delay elements 12, the phase detector 2 can align the rising edge of the signal on the XCLK signal line 8 with the rising edge of the signal on the DQ signal line 24.
FIG. 2 is a timing diagram for the synchronizing circuitry of FIG. 1. As shown in FIG. 2, the rising edge 26 of the XCLK signal 9, which is carried on the XCLK signal line 8 of FIG. 1, is aligned with the rising edge 28 of the DQ signal 25, which is carried on the DQ signal line 24 of FIG. 1. As is indicated by the arrows shown in FIG. 2, the rising edge 30 of DLLCLK signal 33 (carried on the DLLCLK signal line 32 of FIG. 1) initiates the rise and fall of the DLLR signal 21 (carried on the DLLR signal line 20 of FIG. 1), through the Rise Fall CLK Generator 18 (FIG. 1), which in turn initiates the rising edge 28 of the DQ signal 25. Likewise, the rising edge 34 of the /DLLCLK signal 37 (carried on the /DLLCLK signal line 36) initiates the rise and fall of the DLLF signal 23 (carried on the DLLF signal line 22 of FIG. 1), which in turn initiates the falling edge 42 of the DQ signal 25. For proper data synchronization, the timing difference 46 between the falling edge 44 of the XCLK signal 9 and the falling edge 42 of the DQ signal 25 must be less than the tAC specifications for the system in which the synchronizing circuitry will be used. For the example shown in FIG. 2, the data is firing in a high-low, high-low pattern.
Unfortunately, however, not all synchronizing circuitry components are “ideal”. Variations in layout, fabrication processes, operating temperatures, and the like, result in non-symmetrical delays among the DLL delay elements 12 (i.e., a high to low delay (tPHL) is not equal to a low to high delay (tPLH)). Because tPHL conventionally does not equal tPLH, this also results in a skewed data eye and a larger difference 46 between the falling edge 44 of the XCLK signal 9 and the falling edge 42 of the DQ signal 25. In other words, as shown in FIG. 2, for an XCLK signal 9 having a 55/45 duty cycle, due to inconsistencies in the DLL delay elements 12 (FIG. 1), the DLLCLK 33 and /DLLCLK 37 signals may have a duty cycle of 40/60. Because it is the rising edge 30 of the DLLCLK signal 33 and the falling edge 34 of the /DLLCLK signal 37 from which the rising 28 and falling 42 edges of the DQ signal 25 result, the non-symmetrical delays may result in a non-functional system. Furthermore, because the number of DLL delay elements used is cycle time dependent, the skew and difference 46 are also cycle time dependent. This unpredictable skew is undesirable for reliable high-speed performance.
It is, therefore, desirable to have synchronizing circuitry including a DLL which compensates for, or at least makes predictable, the variations in delay among the DLL delay elements to enable better matching between the XCLK signal and the DQ signal and thus more reliable performance at high speeds.